1. Field of the Invention
The present invention relates to a semiconductor device which has two or more system modules which operate in synchronization with a clock signal and more specifically to a semiconductor device which is adapted to compensate for skew in the clock signal which drives the system modules.
2. Description of the Related Art
Conventionally, a system on silicon chip (SoC) includes two or more system modules different in computing function. These system modules are interconnected by a system bus for data communications among them. Further, the system modules are each controlled by an interrupt control signal produced by another module.
Suppose, for example, that there are a first system module which processes audio data and a second system module which processes image data. Then, the first and second system modules will be different in computing speed. In general, audio data is smaller in data amount than image data; therefore, it is not required for the audio data processing first system module to have a computing speed higher than that in the image data processing second system module. In addition, in some cases there is no need to process audio data while image data is being processed. That is, although the second system module needs to be placed in the operating state at all times, the first system module may be placed in the standby state. For this reason, the second system module is directly supplied with an external supply voltage VCC, but the first system module is supplied, as required, with an internal voltage VINT lower than the external supply voltage VCC.
The first and second system modules are supplied with an external common clock signal CLK. The first and second system modules each contain a logic circuit section, which includes two or more flip-flop and latch circuits. These circuits are clocked by the clock signal. If the arrival times of the clock signal at the flip-flop and latch circuits are displaced, that is, if there is a skew in the clock signals, data in the flip-flop and latch circuits cannot be transferred correctly. This causes malfunction of the logic circuit section.
In general, the timing of change of data with respect to change of the clock signal is designed with setup and hold time margins added. If skew in the clock signals in the whole system exceeds the setup and hold time margins, malfunction of the logic circuit section is caused. For this reason, buffer circuits or delay elements are inserted in paths over which the clock signal propagates in order to make uniform the arrival times of the clock signal at the flip-flop and latch circuits even if the lines over which the clock signal are propagated differ in length and load capacitance.
As described above, the internal voltage VINT applied to the audio data processing first system module is set lower than the external supply voltage VCC. The internal voltage VINT is produced by a stepdown circuit embedded in a chip. Depending on the operating conditions of the stepdown circuit, the internal voltage VINT may vary. The operating conditions of the stepdown circuit include temperature, process conditions, and the value of current dissipated by the first system module. When the internal voltage VINT is high, the propagation speed of the clock signal in the first system module increases and vice versa.
In general, skew in two or more clock signals which are driven with different supply voltages is greater than that in clock signals driven with the same supply voltage. For this reason, a problem arises in that skew in the clock signal in the whole system will increase according to variations in the internal voltage VINT.
As a related technique, there is a technique which provides two or more zones on an integrated circuit with clock buffers adapted to delay a reference clock signal in time and involves comparing zone clock signals output from the clock buffers in adjacent zones through a phase comparator and controlling the amount of delay introduced by the clock buffer in a particular zone according to a control signal produced by the phase comparator (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-274341).